Recently, the usage of non-volatile memory comprising a semiconductor device capable of rewriting data and retaining data stored therein even while the device is un-powered has become increasingly popular. Flash memory is one example of non-volatile memory. A typical flash memory is provided with a transistor which operates as a memory cell and includes a floating gate or an insulating film called a charge storage layer for accumulating electrons used to store data. Flash memory with a SONOS (Silicon Oxide Nitride Oxide Silicon) structure for accumulating the electrons in a trap layer of an ONO (Oxide Nitride Oxide) film has been introduced as the flash memory using an insulating film as the charge storage layer. U.S. Pat. No. 6,011,725 discloses a flash memory with a SONOS structure, which has a virtual ground type memory cell where the switching operation is performed between a source and a drain so as to be symmetrically operated.
FIG. 1A is a top view of a conventional flash memory. FIG. 1B is a sectional view taken along the line A-A shown in FIG. 1A. FIG. 1A shows a bit line 12 seen through an ONO film 20. A plurality of bit lines 12 extend in a semiconductor substrate 10 as shown in FIGS. 1A and 1B. The ONO film 20 formed of a tunnel insulating film 14, a charge storage layer 16, and a top insulating film 18 is applied on the semiconductor substrate 10. A plurality of word lines 22 which extend to intersect with the bit lines 12 are formed on the ONO film 20. The bit line 12 serves as both a source and a drain, and the word line 22 also serves as a gate. In the case where the bit lines 12 (B1) and 12 (B2) are set to the source and the drain, respectively, a high electric field is applied to the region between the source and the drain to store electrons in a charge storage region C1. Meanwhile, electrons may be stored in a charge storage region C2 by switching the source and the drain. In this way, the source and the drain may be symmetrically operated to form two charge storage regions in the charge storage layer 16 between the source and the drain of a single transistor. This makes it possible to record two bits in the single transistor.
A general trend in the development of semiconductor devices has been to miniaturize (e.g., reduce the size of) the devices. Typically, this is accomplished by reducing the underlying components comprising the semiconductor device, such as the transistors. However, in order to miniaturize a memory cell, the space between adjacent bit lines in the transistor has to be reduced. As the bit line is formed by diffusing impurities, the impurities are required to be shallowly buried to reduce the space between the bit lines. Subsequently, the bit line is formed to have a small depth.
Unfortunately, when the depth of a bit line is small, some of the electrons jump over the bit line to proceed toward the adjacent cell. FIG. 2, depicts the case where the bit line 12 has a small depth. As shown in FIG. 2, the bit line 12 (B1) is connected to the ground (hereinafter referred to as GND), and the bit line 12 (B2) receives a voltage of +4V, for example. The word line 22 receives a voltage of +9V. Otherwise, the structure is identical to that of the one shown in FIG. 1B. In FIG. 2, electrons are accumulated in a charge storage region C3 in a charge storage layer 16 under a hot electron effect. When the depth of the bit line 12 is small, some of the electrons jump over the bit line 12 (B2) to proceed toward the adjacent cell. A voltage of +9V is applied to the word line 20 common to the adjacent cells. The electrons which have jumped over the bit line 12 (B2) are accumulated in a charge storage region C4 of the adjacent cell. TPD (Transient Program Disturb) occurs when the electrons jump over the bit line 12 so as to be stored in the charge storage region of the adjacent cell. Reduction in the space between the bit lines 12 may cause the TPD, and it is thus difficult to miniaturize the memory cell.